The present relates generally to monolithic integration of optoelectronic and electronic devices. More particularly, the invention relates to monolithic integration of DOES and HFET devices.
A number of recent publications disclose the desirability of integrating both optoelectronic devices and electronic devices on a single monolithic substrate. See for example Wada et al, IEEE Journal of Quantum Electronics, Vol. QE-22, No. 6, June 1986, pp 805-821; Nakamura et al, IEEE Journal of Quantum Electronics, Vol. QE-22, No. 6, June 1986, pp 822-826; Maeda et al, Hitachi Review, Vol. 35, No. 4, 1986, pp 213-218; and Shibata et al, Appl. Phys. Lett. 45(3), Aug. 1, 1984, pp 191-193. These advantages include higher speed operation and better noise performance due to reduction of parasitic reactances, and higher system reliability and simpler system assembly due to reduction of system parts counts.
Unfortunately, the semiconductor layers required for the construction of most optoelectronic devices differ from the semiconductor layers required for the construction of most electronic devices. As a result, optoelectronic devices have been integrated onto the same substrate as electronic devices by growing the semiconductor layers required for optoelectronic devices onto a semiconductor substrate, etching the grown layers to expose the semiconductor substrate at locations where electronic devices are desired while masking the grown layers at locations where optoelectronic devices are desired, and forming electronic devices in the substrate and optoelectronic devices in the grow layers.
This procedure is rather complicated and has significant disadvantages. In particular, the grown layers protrude beyond the surface of the exposed substrate so that masks used to define the electronic devices are held away from the substrate surface during photolithography. This limits the resolution of the photolithography process and correspondingly limits the density of the electronic devices. Moreover, the electronic devices are formed at an etched surface of the substrate. The etching process degrades the quality of this surface and this affects the functioning of the resulting electronic devices. In particular, field effect transistors (FETs) formed at such an etched surface typically have nonuniform threshold voltages. Both of the above effects limit the yield of such integration processes.
In another known method for integrating optoelectronic devices onto the same substrate as electronic devices, a groove is formed in the substrate and the semiconductor layers required for optoelectronic devices are grown only in the groove. Optoelectronic devices are then formed in the groove, while electronic devices are formed on the substrate alongside the groove. Unfortunately, the groove required for this process must be made 5 microns to 10 microns deep in order to accommodate all of the semiconductor layers required for optoelectronic devices, and a step discontinuity of this magnitude impairs the resolution of photolithographic processes used to define the optoelectronic and electronic devices.
Recent publications have disclosed a family of electronic and optoelectronic devices including the Bipolar Inversion Channel Field Effect Transistor (BICFET), Heterojunction Field Effect Transistor (HFET), Heterostructure Junction Field Effect Transistor (HJFET), HFET PhotoDetector (HFETPD) and Double heterostructure OptoElectronic Switch (DOES). See for example Taylor et al, IEEE Trans. Electron Dev., Vol. ED-32, No. 11, November 1985, pp 2345-2367; Taylor et al, Electron. Lett., Vol. 22, No. 15, July 1986, pp 784-786; Taylor et al, Electron. Lett., Vol. 23, No. 2, January 1987, pp 77-79; Simmons et al, Electron. Lett., Vol. 22, No. 22, October 1986, pp 1167-1169; Simmons et al, Electron. Lett., Vol. 23, No. 8, April 1987, pp 380-382; Taylor et al, Appl. Phys. Lett. 50(24), June 1987, pp 1754-1756; Taylor et al, J. Appl. Phys. 59(2), January 1986, pp 596-600; Taylor et al, Appl. Phys. Lett. 48(20), May 1986, pp 1368-1370; Taylor et al, Appl. Phys. Lett. 49(21), November 1986, pp 1406-1408; and Simmons et al, IEEE Trans. Electron. Dev., Vol. ED-34, No. 5, May 1987, pp 973-984.